1. Field of Invention
The invention relates to a magnetic random access memory, and more particularly, to the operation of an asynchronous MRAM with an internally generated clocking plus and an ATD (Address Transition Device) circuit.
2. Description of Related Art
Typical Magnetic Random Access Memory, MRAM, structures have a nonmagnetic layer sandwiched between two ferromagnetic films. The two ferromagnetic films are also known as magnetic thin films. The MRAM employs the magneto resistive properties of this structure to store data. In each storage element, an MRAM employs two lines, commonly termed a word line and a sense string, in order to detect the magnetization direction of these magnetic thin films. Each string comprises a magnetic thin film that serves as a memory element, and the word line generally addresses multiple sense strings. Magnetic thin films that have a parallel moment have a low resistance and are typically assigned the ‘1’ state. Magnetic thin films having an anti-parallel moment have a high resistance and are typically assigned the ‘0’ state, but may also be assigned to the ‘1’ state.
During a read operation, a word current passes through the word line causing the magnetic layers in the sense string to rotate, thereby changing the resistance in the sense string. A sense current passes through the sense string. A sense line receives the signal from the sense string. A differential amplifier compares the signal from the sense line to a reference line to determine whether a one resistance or a zero resistance is stored in the MRAM. A differential amplifier notes the change in voltage across the sense line to determine resistive state of a storage element.
With any asynchronous circuit, a signal transition on any input will elicit an internal response. An asynchronous MRAM is no different in the uncontrolled case. Being a memory structure, an MRAM has two operational cycles, namely a read cycle and a write cycle. If an input such as an address signal were to change during the critical part of a write operation, neither could its completion nor the address location of the operation be guaranteed. It is possible to create indeterminate states within the MRAM itself at indeterminate locations under these conditions. If the address signal changed during a read operation, then the output would become an indeterminate state as the actual address location being read could transition during the read cycle.
Prior solutions involve other internal clock pulse generation schemes and circuitry that are not suitable for MRAM due to limited functionality and the unique demands of a asynchronous magnetic random access memory. In the traditional usage an address transition detector is used for memory address signals.
What is needed is a transition detector for other signals such as the data signals as well as the chip enable (NCE) and write enable (NWE) signals.